As a technical consultant with my own small company, I can't count on job security from government interventionjust not enough votes there. In order to keep money coming in, I have to rely on reinventionby learning new techniques for solving problems.

As the number of execution cores in multi-core processors continues to increase, software that is not properly threaded will suffer performance penalties and become less competitive in the marketplace. Decision makers at software companies should act now to position their products for success as hardware parallelism grows exponentially.

As you probably know by now, to get the maximum performance benefit from a processor with Hyper-Threading Technology, an application needs to be executed in parallel. Parallel execution requires threads, and threading an application is not trivial. What you may not know is that tools like OpenMP* can make the process a lot easier. This is the first in a series of three white-papers that teach you, an experienced C/C++ programmer, how to use OpenMP to get the most out of Hyper-Threading Technology. This first paper shows you how to parallelize loops, called work sharing.

A recent Threading Building Blocks poll reported that 33 percent of TBB users have used one or more of the algorithms (parallel_for, parallel_reduce, pipeline, etc.). This was more than any other category except "None of the above (I'm just getting started)," which also had 33 percent.

Intel® Threading Building Blocks (TBB) was designed to simplify programming for multi-core platforms. By introducing a new way of expressing parallelism, developers can focus on efficient scalable parallel program design and avoid dealing with low level details of threading. This talk will focus on the taskbased approach to threading of the Intel® TBB. We will show step by step what needs to be done in order to take advantage of the TBB task-based programming model in your code.

As you know, OpenMP* contains a very powerful set of pragmas that help you parallelize a loop. What you may not know is that OpenMP can be used to thread more than just loops. When the "parallel for" construct falls a little short, OpenMP has additional pragmas, constructs, and function calls that come to the rescue. This second paper, in a series of three, teaches you how to exploit non-loop parallelism and some of the other general OpenMP features.

What does the future hold for concurrency? What will happen to the tools and techniques around concurrent programming? In part two of our series, concurrency guru Herb Sutter talks about these issues and what developers need to be reading to understand concurrency.

Multi- and many-core chips are entering the mainstream—and one of the first software development authorities to take note was C++ expert Herb Sutter. Thanks to his practical insights, a new generation may grok concurrency sooner than previously thought possible.

Performance gains did not come about solely because of increasing transistor densities. They have also relied heavily on another physical factor that is closely related to transistor size: processor clock frequency. Learn what Intel is doing to improve performance even further.

This paper discusses the approach to parallelize the Data Encryption Standard (DES) algorithm with Intel® Threading Building Blocks and how it can scale for future processors.

This whitepaper provides a high-level overview of debugging on Intel processor-based platforms for technical decision makers. It catalogues the relevant debuggers and describes the features and benefits of each with references to additional information.

Explicit threading methods, such as Windows or POSIX threads, use library calls to create, manage, and synchronize threads. Use of explicit threads requires an almost complete restructuring of affected code. On the other hand, OpenMP is a set of pragmas, API functions, and environment variables that enable you to incorporate threads into your applications at a relatively high level. Find where parallelism can be implemented effectively within a serial application.

The industry shift to increasing levels of hardware parallelism through higher numbers of execution cores in mainstream processors requires change on the part of software makers. One key requirement is to look ahead to the hardware resources that are likely to be available in the future and to make appropriate architectural decisions in advance to accommodate them. This paper contributes to the discussion about planning for those developments.

Grid computing based on Web services provides a compelling means for enterprises to create High-Performance Computing infrastructures. Adding to the inherent cost/performance advantages of grid networks based on Intel® Xeon® processors and/or Itanium® processors, building solutions from pre-existing Web services adds efficiency and simplifies the addition of standards-based core functionality to those systems. For those organizations that want expert external guidance in the development of such systems, Intel® Solution Services, Intel Corporation’s worldwide professional services organization, offers assistance that can range from minor decision support to full consulting and design services.