The myth of endless chip progress is cracking. I’m convinced the industry has hit the edge of physics, and the next chapter will be written by places built to test the impossible. One quiet lab in Leuven, Belgium—Imec—shows why the future of computing depends on fresh thinking, new tools, and a willingness to stack devices in three dimensions, not just shrink them in two.
The Stance: Reinvention, Not Increment
We are at the end of easy scaling. The miracle of packing more transistors into a slice of silicon is running out of road. The numbers prove it and the microscopes confirm it. As the speaker put it, chips have reached the Ångström era where transistors are just a few atoms wide—and that’s not a metaphor, it’s a mechanical and thermal crisis.
“We are running into the hard limits of physics… transistors are now literally just a few atoms wide.”
Imec’s answer is not a tweak, but a turn. First, by flipping FinFET sideways into gate-all-around nanosheets. Then, by stacking devices vertically into CFET, placing p- and n-type transistors on top of each other. That move is the first true push into 3D logic density.
“For the first time in history, two transistors stand on top of each other… opening the door to a new era of computing.”
My view is simple: CFET buys time, not salvation. The only sustainable path forward is system-level progress—chiplets, advanced packaging, and light-speed communication—supported by neutral research hubs where rivals share risk and tools.
Evidence From The Lab Floor
The case for reinvention comes from the brutal details of making atoms obey. FinFETs bent and snapped as fins got thinner. Nanosheets fixed that, but density hit a wall again. CFET restores headroom by stacking, yet it also demands a new class of machines and materials. As Imec’s Serge Biesemans told the camera, what looks “simple” took years off his life.
“Some people say Moore’s law is an equipment capability law… if the tool does not exist… you would not be able to physically build the complicated structure.”
That is why EUV scanners cost over $250 million each and why the next High-NA EUV tool fills a hall. New etch, deposition, epitaxy, backside power delivery—none of this is optional. The industry now treats equipment as the limiting factor as much as device physics.
Then comes the inspection gauntlet. A Scanning Electron Microscope reveals features smaller than viruses, but risks destroying the sample in seconds. A Transmission Electron Microscope reaches atomic detail—thin lamella slices, painstaking prep, and a live view of channels about 30 atoms thick. That’s not hype; it’s the cliff edge.
Why Systems Beat Shrinks
The growth curve has already shifted. Performance no longer comes mainly from smaller transistors. It comes from the package: multiple chiplets placed side by side and, soon, stacked. The bottleneck is communication. Today, chiplets shout over centimeters. Light can fix that.
Silicon photonics already links racks in data centers. Imec is pushing it into packages by cutting power, stabilizing lasers, and testing promising materials like barium titanate on 300 mm wafers. If they succeed, the speed and efficiency of light-based links could reach laptops, not just GPU clusters.
Imec is also working to stack entire wafers, aligning “streets” layer to layer to strip out wiring overhead. That’s a path to a true 3D computing cube—and to mixing different chip types and materials in one tight package.
- Short term: Gate-all-around and CFET extend scaling.
- Mid term: Chiplets, advanced packaging, and photonics lift system performance.
- Long term: New materials and device physics race for viability.
I see no single silver bullet here. Imec’s bet is parallel bets: ternary logic, reversible logic, spintronics, cryogenic CMOS, graphene, 2D crystals, carbon nanotubes. Some may never leave the lab. But the neutrality of a nonprofit pilot line means the best ideas get tested early, at scale, and shared.
The Counterpoint—and Why It Fails
Skeptics say shrinking will keep grinding forward. But heat, leakage, and fabrication risk are not hand-waved away. Costs explode, yields suffer, and teams hit equipment limits. Even with CFET, the curve does not return to the old exponential. The game is now integration, interconnect, and energy per bit.
Conclusion: Fund The Places That Try The Impossible
If we want progress to continue, we must back pre-competitive research and system-level design. That means more Imec-like models, more pilot lines, and aggressive support for packaging, photonics, and new devices.
My call to action: push your company, your lab, or your elected leaders to invest in neutral shared infrastructure, not just product fabs. Ask your teams to measure wins in energy per compute, not just clocks and cores. The miracle of simple shrinking is fading. The next leap will be built—layer by layer—by those willing to rethink the entire stack.
Frequently Asked Questions
Q: What makes CFET different from earlier transistors?
CFET stacks p- and n-type devices vertically, doubling logic density without shrinking features in 2D. It solves stability issues that limited thin fins and nanosheets.
Q: Why can’t we just keep shrinking transistors?
At atomic scales, structures bend, heat surges, and leakage rises. Tools struggle to build and measure features a few atoms wide. Cost and yield become the real barriers.
Q: How do chiplets improve performance?
They break a giant chip into smaller tiles and connect them in one package. This boosts yield and flexibility. Better interconnects cut latency and reduce energy per bit.
Q: Is silicon photonics ready for laptops and phones?
Not yet. Current parts consume too much power and are temperature sensitive. Research at places like Imec focuses on materials and designs that lower that power cost.
Q: What comes after CFET if scaling stalls again?
Expect deeper 3D stacking, wafer-to-wafer integration, and experiments with new materials and logic types. No single path is guaranteed, so multiple approaches are being tested in parallel.
