We like to think the AI race is about GPUs. It is not. It is about light. The smallest chips only exist if we can print features smaller than dust. My view is simple: the industry must double down on today’s extreme ultraviolet (EUV) tools while urgently preparing for a leap into particle-accelerator light sources.
This debate matters now because demand is exploding, fabs cost tens of billions, and physics is closing in. Transistors shrink. The tools that make them swell to stadium size. That tension will decide who leads the next decade.
The Case for a New Light
EUV lithography at 13.5 nanometers was a moonshot that worked. It made 5 nm and 3 nm real. But it is straining. Efficiency is miserable. Reliability is precious. And randomness creeps in at the smallest scales.
“Some estimates place the wall plug efficiency below 0.1%.”
“At 3 nanometers… fabs start approaching stochastic limits.”
That is the quiet crisis. At these sizes, you fight probability itself. Photons arrive too sparsely and too irregularly. Tricks like multi-patterning pile on cost and risk. The fix many engineers now eye is a different source of light: free-electron lasers (FELs) fed by particle accelerators.
FELs do not use exploding tin. They whip electrons through magnetic tunnels and harvest the emitted radiation. The promise is volume and control. A single FEL could flood many scanners with EUV at once. And unlike fixed 13.5 nm, FELs are tunable.
“Some FEL facilities already operate around 6 nanometer… and some even below 1 nanometer.”
If tunability reaches production, chip factories change from machines that print chips into campuses that engineer light.
Three Paths, One Goal
Different regions are pursuing different answers to the same problem. The strategies tell you who is trying to win, and how.
- United States: xLight aims to swap today’s tin-plasma source with an accelerator-fed source, keeping scanners and mirrors intact. Target: more EUV power, lower running cost.
- Japan: KEK is focused on energy recovery linacs. Recycle the electron beam’s energy to slash power waste and scale to kilowatts of EUV.
- China: Tsinghua-linked SSMB backs a large storage ring for continuous, centralized EUV. One ring to feed many scanners. Scale over compactness.
Each path tries to fix the same choke point: make more reliable light at lower cost, then share it across many tools.
The Counterargument That Still Wins Today
There is a reason ASML still rules. Their EUV works inside real fabs, all day, every day. Uptime beats elegance. A beautiful accelerator that stalls at 3 a.m. is useless next to a tin-droplet system that soldiers on.
“The semiconductor industry rewards the machine that keeps running at 3 in the morning.”
I respect that view. I share it. You do not bet a multi-billion-dollar line on a lab trick. Even ASML weighed accelerator paths and stuck with plasma. That should give every investor and policymaker pause.
What Should Happen Next
We cannot wait for miracles. We can prepare for them. Here is how I would proceed while keeping factories running:
- Back near-term EUV upgrades that improve power and uptime without rewriting the fab.
- Fund dual-track pilots for FEL sources that can plug into current scanners.
- Stress-test centralized light farms with redundancy, not single points of failure.
- Push photoresist and metrology advances to tame shot noise at 3 nm and under.
- Train a new class of engineers who speak both lithography and accelerator physics.
The goal is steady output today and a glide path to accelerator light tomorrow. We need both.
My Take
Who controls the light will control the next era of chips. ASML’s tin-plasma EUV remains the workhorse. But the ceiling is visible. FEL-based sources could break it by supplying more photons, on demand, and at dialed wavelengths. If America makes it compact, Japan makes it efficient, and China makes it massive, the winning model will mix those traits with ruthless reliability.
Here is the paradox we must accept: chips get smaller; the machines that make them get huge. If that is the price of progress, pay it. Build the light. Build the backups. Keep the wafers moving.
Call to action: fund pilot lines now, align standards for shared light sources, and demand uptime metrics from every FEL project. Do not wait for perfection. Insist on progress you can ship.
Frequently Asked Questions
Q: Why is EUV efficiency such a problem?
Most input energy never reaches the wafer. That waste drives high power needs, heat, and cost. It also limits how fast you can print.
Q: What makes shot noise so damaging at 3 nm?
Feature sizes are so tiny that small photon count swings cause missing or malformed lines. Randomness starts to show up as real defects.
Q: How would a free-electron laser plug into a fab?
In some designs, a central light source feeds multiple scanners through beamlines. The scanners stay. The source changes.
Q: Isn’t a centralized light farm a single point of failure?
Yes, unless built with redundancy. Multiple beamlines, hot spares, and failover plans are required to keep wafers flowing.
Q: Will accelerator-based EUV arrive in time for the AI surge?
Not for the near term. ASML’s systems will carry the load now. Accelerator pilots should target the next wave of nodes and capacity.
